As the packaging density and complexity of integrated circuits continues to increase, the ability to test such circuits becomes a more complicated and time consuming task. Typically, the circuits are packaged as DIPs (e.g. sixteen to sixty-four pin components) which are to be assembled on a printed circuit board as part of an overall system-functional unit. Prior to board assembly, the various DIP components are subjected to a prescribed device verification procedure, usually by way of functional testing via the pin contacts of the DIP. Because each pin contact of the DIP is coupled to a prescribed circuit path within the integrated circuit, proper testing of the circuit requires that the DIP be completely inserted into the contact coupling receptacle of the test apparatus with the proper pin orientation. Moreover, because of the limited time window during which each device is able to be tested in terms of a practical throughput of the testing system, full functional testing has not been generally possible for a number of devices such as LSI components, and large ROMs and RAMs, so that an alternative verification procedure is required.